I. Technical Field
The present invention relates to a planarization composition which is particularly useful for thinning, polishing and planarizing integrated circuitry deposited on semiconductor wafers which have an inter-layer dielectric material deposited on their surfaces to form insulating dielectric films. The thinning, polishing and planarizing serves to remove a portion of the dielectric film so as to flatten and smoothen the deposited dielectric surface, and further to remove excess deposited dielectric material during the formation of shallow trench isolation structures. The invention also relates to a thinning, polishing and planarizing apparatus and method for carrying out the thinning, polishing and planarizing process to flatten and smoothen the dielectric film and to remove excess deposited dielectric material during the formation of shallow trench isolation structures.
II. Discussion of Related Art
In semiconductor processing, it is common to deposit a thin film of an insulating material, for example a dielectric such as doped or undoped oxides of silicon, over already existing dielectric thin films interspersed with other exposed semiconducting and conducting integrated circuit features such as a semiconductor trenches lined with a thin thermal oxide and high density plasma oxide, tungsten silicide/polysiliconlgate structures or titanium/aluminum/titanium nitride structures. The deposited insulating thin film acts as an electrical isolation layer between semiconductors and conducting pathways adjacent to and under the insulating thin film. The deposited material constitutes what is commonly referred to as a shallow trench isolation structures or an interlayer dielectric insulator. When this process is carried out, a thin coating of the material being deposited to fill, and therefore electrically isolate, the semiconductor and inter-gate and inter-metal gaps is deposited globally on the upper surface of the remaining exposed insulating thin films, semiconducting and conducting pathways. The deposited dielectric material is deposited to sufficiently fill the gaps between adjacent semiconducting gate structures and metal conducting pathways, thus partially planarizing the upper surface.
For shallow trench isolation and gate structures, it is preferable to fill the gaps and continue to deposit the dielectric so that there is an excess amount of dielectric material deposited substantially above the gaps. This process is commonly called a gap-fill process. Depending on the type of integrated circuit there may be from one to three types of dielectric materials deposited to complete the gap-fill process, such as the thermally grown and high density plasma CVD deposited oxides used for shallow trench isolation. Each type serves a unique purpose. However, after this dielectric gap-fill process, the planarity of the resultant gap-filled surface is not planar enough to be used as an imaging plane upon which the next pattern of circuitry is defined by photolithographic techniques. A surface that is not highly planar and that has a high scratch density and surface roughness will yield circuit features of varying degrees of quality that will have direct impact on device performance and yield. This is due to the non-planar scratched and rough regions being "out-of-focus" relative to the planar unscratched and smooth regions. Thus, this non-planar dielectric surface must be planarized and surface roughness and scratches be reduced further prior to carrying out the IC patterning process.
The removal of layers of this nature is generally carried out by a thinning, polishing and planarizing operation utilizing a hard surface of a polishing pad and a polishing slurry which wets the pad and is frictionally moved against the excess deposited dielectric surface to be removed. The slurry generally includes silica particles as the abrasive material along with a liquid carrier. Basically, the silica and the liquid carrier are respectively hard enough so as to abrade away the still unplanarized dielectric thin film. The aforementioned method planarizes by mechanical means only. The result, however, is a planarized surface that has a substantial number of scratches and a surface roughness that is not suitable for the manufacture of integrated circuits which utilize sub 0.3 5-micron geometries. Further, in addition to the polishing and planarizing rates for this method being too low to be production-worthy, this type of thinning, polishing and planarizing slurry is considered too dirty having high levels of potential yield-limiting metal ion impurities incorporated in the liquid carrier and the silica slurry abrasive.
It is well known to combine the abrasive and liquid carrier with a reactive chemical constituent. This method is commonly referred to as chemical mechanical polishing (CMP). In this process, more rapid thinning, polishing and planarizating can occur through utilization of an abrasive material, generally alumina or silica, along with a liquid carrier and a compound which is corrosive or oxidative toward or will dissolve the substrate. For example, U.S. Pat. No. 5,391,258 of Brancaleoni, et al. discusses such a process for enhancing the polishing rate of silicon, silica or silicon-containing articles including composites of metals and silica. The composition includes an oxidizing agent along with an anion which suppresses the rate of removal of the relatively soft silica thin film. The suppressing anion may be any of a number of carboxylic acids. Alumina is used as the abrasive material.
It is also known to utilize another abrasive material, specifically silica of very small size, to polish substrates such as rough cut silicon wafers prior to beginning their processing into integrated circuit devices. As an example, Shimizu, et al., in U.S. Pat. No. 4,842,837, teaches a process for producing fine spherical silica having a particle size of 0.5 m and less. The particles are mono-dispersed whereby polishing of the relatively soft, chemically reactive silicon wafer surface can be carried out to produce a substantially flat wafer surface. The resulting colloidal silica was proposed as a polish for silicon wafers, specifically silicon wafers but not interlayer dielectrics such as doped and undoped thermally grown or CVD deposited oxides of silicon. Further, the resulting colloidal silica had unacceptably high ammonia and alcohol contents that prohibited them from being used broadly in silica wafer polishing and frm being used for interlayer dielectric and shallow trench isolation CMP.
U.S. Pat. No. 5,376,222 discloses the use of colloidal silica in an alkaline solution for polishing a silica film on a semiconductor. The polishing solution includes a cation of an alkali metal, an alkaline earth, or an ammonium ion.
U.S. Pat. No. 3,877,183 discloses the use of precipitated silicates and/or silicofluorides as polishing substances for semiconductor materials. These polishing substances are utilized to polish the semiconductor, namely, silicon.
A very real problem exists with respect to polishing materials such as insulating dielectric films without scratches and sufficiently low enough surface roughness and post-planarization surface and dielectric film cleanliness. Insulating thin films are deposited within the channels which fills the channels but still leaves the dielectric thin film surface not planar enough. Further, insulating thin films are deposited to substantially fill shallow trenches. The trenches are intentionally over-filled and then polished and planarized back to the plane of the filled trench. So, what is commonly referred to as a planarization process, is implemented to remove, layer by layer, the "bumpiness" of the dielectric thin film, and to remove the globally deposited oxide trench over-fill back to the plane of the oxide filled trench.
Today's state of the art planarization process, although at one time was sufficient enough to fully planarize the dielectric surface, is no longer sufficient. Scratches (macro-scratches) and haze (micro-scratches and light-point defects), which were once not considered yield-limiting defects, are considered yield-limiting defects today and today's benign scratches and haze most likely will become more substantial yield-limiting factors with tomorrow's more advanced, higher performance, integrated circuits. Relatively speaking, planarized and polished dielectric surfaces must be smoother, cleaner, scratch-free and more planar than they are today. Particle size distribution and the shape of the abrasive are the two of the most important factors which affect scratch density and haze. Today's abrasives used for dielectric planarization are almost exclusively fumed silica whose particle size distribution and shape cause undesirable surface scratches and haze. The particle size distribution of fumed silica and alumina can range from 24 to greater than 300 percent. More recently, the industry has been testing precipitated silicas, as opposed to fumed silicas, for dielectric CMP. With precipitated silica slurries the surface roughness and scratch levels are substantially improved over fumed silicas but today's commercially available and most widely used are manufactured from sodium silicate or potassium silicate. Sodium and potassium are considered the most dangerous yield-limiting contaminants to integrated circuits during their manufacture and therefore the use of precipitated silicas have not gained industry-wide acceptance. Further, there are other high levels of yield-limiting impurities in precipitated silica slurries such as alkaline earth, transition metal and heavy metal ions that make precipitated silicas undesirable as a thinning, polishing and planarizing dielectric slurry. Because today's fumed silica and alumina slurries are so dirty, an extensive and costly post-thinning and planarizing cleaning process must be implemented to remove only some of the slurry-induced, yield-limiting surface and sub-surface impurities.
At the start of a typical prior art thinning and planarizing (CMP) process, one or more dielectric layers are exposed. After a substantial amount of thinning, polishing and planarization, the bumps and oxide overfill remaining are sufficiently removed so as to produce a planarized surface. With the conventional fumed silica-based thinning and planarizing process, the dielectric surface is planarized while scratches, haze and surface impurities remain on the surface. For instance, the most widely used slurry thins and planarizes with a particle size distribution of 23 to 300 plus percent and impurity levels exceeding 50,000 ppb. The result of the thinning and planarizing process is an unpredictably rough and scratched surface that has unacceptably high levels of surface and sub-surface yield-limiting impurities such as sodium, potassium, aluminum, iron, and chlorides.
Integrated circuit manufacturers have been asking fumed and precipitated silica slurry manufacturers to improve today's slurry particle size distribution and purity but without much success. Although the fumed silica abrasive has higher purity than today's seldom used precipitated sodium silicate slurry, it does not have the narrow particle size distribution that can be achieved with a precipitated sodium silicate slurry. With a sodium silicate slurry, particle size distributions can be less than 10 percent, thus yielding a much improved surface haze and scratch density, but this improved performance is accomplished at a relatively inferior impurity concentration level. Especially for the CMP of shallow trench isolation structures, such as a sodium or potassium silicate slurry has the potential to degrade device yield more substantially than any defects traceable to surface scratches and haze. Thus today's precipitated silica slurries, based on sodium silicate, have not gained substantial market acceptance.
To date, there has not been a satisfactory solution to the future need for improved surface roughness, reduced scratch density and improved slurry purity for interlayer dielectric thinning and planarization.
Today's conventional fumed silica and alumina-based dielectric thinning and planarizing slurries have a broad particle size distribution from .+-.24 percent to .+-.300 plus percent. The higher the particle size distribution, the greater the surface roughness and scratches. Integrated circuit manufacturers are finding today that they must reduce particle size distribution because of a future requirement that they use photolithography technology having a shallower depth of focus. Having a requirement for a shallower depth of focus in the future also requires that the surface of the integrated circuit, as it is being manufactured, have improved surface roughness and less scratches. Any one of the above parameters, if not improved, can cause future, more advanced integrated circuits to fail. To date, there has been a substantial effort to reduce the particle size distribution and therefore reduce haze, improve surface roughness and reduce scratch density but without the substantial success required to meet tomorrow's performance requirements (depth of focus) dictated by photolithography.
Furthermore, because of the still high impurity levels in today's conventional fumed silica slurries, it has been shown that they cause defects and circuitry failure. Further, it has been shown that the higher the purity of the slurry, the lower the normalized integrated circuit defect density. Accordingly it would be highly desirable to develop a polishing composition which is of a higher purity in order to reduce the post thinning and planarization integrated circuit defect density.
Because of the above shortcomings of today's conventional silica-based thinning and planarizing dielectric CMP slurry, the industry has been looking for an improved thinning and planarizing system which leads to improved surface roughness scratch density and slurry purity, while maintaining the same degree of safety. Although an alkosol has the particle size distribution and purity levels consistent with the what will be required by tomorrow's more advanced integrated circuit technology, the polishing rates are to low to be production-worthy. Further, the current alkosols contain at least 30 wt percent of alcohol which is a concentration too high to be used safely in an integrated circuit manufacturing plant. Therefore, the current alkosols, once believed to be the answer, suffer from productivity and safety shortcomings.